1. Field of the Invention
This invention relates generally to the testing of un-diced semiconductor chips in wafer form. More particularly the present invention is directed to an arrangement that will provide for the testing of a plurality of such un-diced chips on a semiconductor wafer while using a minimum number of tester interfaces or contacts while simultaneously providing at least two communication paths coupling each such un-diced chip to two different tester interfaces.
2. Background of the Invention
In a typical semiconductor wafer, a plurality of integrated circuits is formed therein as individual blocks or chips which are electrically separated from one another by suitable dicing paths or kerfs lying between adjacent chips. Once the chips are formed in the wafer and while they still are in situ on the wafer, they are tested to determine which are functional and which are not. After testing the wafers are cut into individual chips by cutting the wafer along the dicing paths or kerfs. Any one of a variety of dicing techniques generally known to the art can be used. Once so separated each good chip is then packaged and sold and any failing chips are discarded.
In one present day testing procedure, a tester having a set of probes identical with the set of contact pads on each chip is individually placed in contact with the pads on a single chip, the chip is tested and then the tester probes are removed from the tested chip and moved to an adjacent chip that is to be tested. Because each chip must be individually probed, this procedure is difficult and time consuming.
To avoid the costs of individually probing and testing each chip as above described, large specialized testers capable of probing and collecting data from several chips simultaneously were developed. As might be expected, the complexity of these machines has increased proportional to the size and complexity of the chips to be tested thus increasing the cost and complexity of the test procedures. Also, the number of chips that may be tested simultaneously with such machines is limited by the size and number of the probes necessary to contact the chips being tested.
In a first attempt to overcome such problems, surface wiring, that would contact each chip so that data could be extracted therefrom, either was deposited in the kerf between the chips or formed on an insulated overlay that can be placed atop the chips. However, as the size of the wafers increased the number and size of the chips became proportionally greater and the number, length, extent and reliability of these wiring or communication paths existing between the tester and each of the chips to be tested became not only still more complex and more prone to failure but the power and cooling requirements also increased. To alleviate these problems, each chip to be tested was then provided with a portion of the required test logic and arranged in sets with each set provided with a respective BIST (built in self test) engine. This solution however increased the wiring density in the kerfs between the sets and further complicated the electrical circuitry of each chip and thus further increased the probability of chip failure while simultaneously causing the size of each chip to be correspondingly enlarged. This resulted in a reduction in the number of chips that can be formed on each wafer. Still further, because this approach requires that the data be extracted serially from each chip through the deposited wiring, not only is the required test time extended but any defects in the wiring or in the added circuitry caused good chips to be erroneously identified as failures.